As semiconductor devices become more highly integrated, the widths of wirings and intervals between the wirings on these device have been greatly reduced. The size of structures grown on the devices and the dimensions of bit lines have also been greatly reduced.
Contacts are highly conductive films that connect isolated regions of a device. Semiconductor contacts may occupy considerable portions of the semiconductor device because the contacts typically require both an alignment margin and an isolation margin. As a result, the size of the contact may become one of main factors that determine the size of a cell in a semiconductor memory device, such as a DRAM device.
Conventional methods for forming a contact typically cannot be used to form a very small contact. Moreover, with semiconductor memory devices that include a plurality of conductive films, interlayer dielectrics are generally interposed between the conductive films which makes forming the contact more difficult because a vertical interval between the conductive films is very large. To address these difficulties, a method for forming a contact using a self-aligned process has been developed in order to provide semiconductor memory devices having reduced cell sizes.
Generally, when forming a self-aligned contact, the contact size is varied based on the heights of the adjacent structures, the thickness of the insulation film where the contact is formed, and the etching process used to form the contact. Contacts formed using the self-aligned contact method may be smaller than contacts formed using a conventional process because the self-aligned contacts do not require an alignment margin. The method for forming the self-aligned contact is generally performed using the etching selectivity between an oxide film and a nitride film and by employing an anisotropic etching process.
Unfortunately, when a contact pad that contacts a source/drain region between gate electrodes is formed using the self-aligned process, nitride spacers that are formed on the sidewalls of the gate electrodes and nitride masks that are provided on the gate electrodes may be partially etched when the oxide film that is positioned between the gate electrodes is etched. The gate electrodes may be exposed during the etching of the oxide film because of shoulder margins associated with the nitride spacers and the nitride mask. As a result of this unintended etching, the gate electrodes may be connected to the contact pad, thereby causing an electrical short between the gate electrodes and the contact pad.
To prevent such an electrical short, the thickness of the nitride spacer and the thickness of the nitride mask may be increased. However, when the thickness of the nitride spacer increases, the resistance of the contact also increases because the contact area between the contact and the source/drain region decreases. In addition, when the thickness of the nitride mask increases, voids may be easily generated in the oxide film because the gap between the gate electrodes may be completely filled by the oxide film.
A method for forming a contact pad at exposed portions of a silicon substrate between gate electrodes has been suggested in which silicon contact pads are grown using a selective epitaxial growth process. However, the silicon contact pad grows not only along <1 0 0> crystalline direction that is perpendicular to the substrate, but also along <110> crystalline direction that is parallel to the substrate. Thus, when this method is used, adjacent contact pads may become connected to each other to generate an electrical short.
To overcome this problem, an insulation film may be formed between epitaxially grown films in order to insulate the epitaxially grown films from one another after the epitaxially grown films are selectively formed on the substrate to have limited dimensions along a direction parallel to the substrate. Korean Patent Laid Open Publication No. 2002-53542 discloses a method for forming a secondarily epitaxially grown film selectively on the above-mentioned epitaxially grown films. However, the insulation film may hardly form between the epitaxially grown films, and even when the insulation film exists on the epitaxially grown films, the secondarily epitaxially grown film may not be formed on the epitaxially grown films. If the insulation film is over-etched to prevent the above-mentioned problem, upper portions of the epitaxially grown films are exposed such that they may not prevent horizontal growth of the silicon during the formation of the secondarily epitaxially grown film.